Hiring Organisation: Apple
Post Name: Power Engineer
Qualification: Bachelor Degree
Work Hours: 8 Hours
Salary: $30 - $50/hour
Location: Dover, USA
Full Job Description:-
Rundown
Envision what you can do here. Apple is where unprecedented individuals accumulate to give them all work. Together we make items and encounters individuals once could never have envisioned, and presently, can't envision living without. It's the variety of those individuals and their thoughts that moves the advancement that goes through all that we do.
Key Capabilities
Graduate degree or unfamiliar identical in Electrical Designing, PC Designing, or related field and 2 years of involvement with the gig offered or related occupation.
- 1 year of involvement in every one of the accompanying abilities is required:
- Prearranging or Programming
- Power Investigation
- Electrical or PC Designing
- Early evening or STA
- PNR streams
Portrayal
Various positions are accessible in West Lake Slopes, Texas. Work widely with Miniature engineers to characterize memory subsystems, perform practicality, make region, recurrence, execution, and power compromises, and plan and equilibrium of the pipeline stages. Working PC helped design or plan programming or hardware to perform and aid all periods of the plan of elite execution chip from Register Move Level (RTL) to last GDSII conveyance. Perform front-end execution undertakings, for example, organized information way plan, combination, rationale equality check, power purpose approval, and static timing examination (STA). Deliberate and team up with the RTL group to perform an achievability examination on recommended microarchitectures, including execution, region, timing, power, intricacy, and exertion. Immediate and coordinate assembling particulars while creating timing limitations for amalgamation, place, and course (PnR), and static timing examination (STA). Make floorplans including pin and full-scale arrangement and power framework. Perform PnR and close the plan to meet timing, region, and power limitations, while working widely with Miniature engineers to characterize memory subsystem, perform achievability, make region, recurrence, execution, and power compromises, and plan and equilibrium the pipeline stages. Coordinate electric power-producing plants and appropriation lines to carry out ECOs to fix timing, clamor, and EMIR infringement, while working with the multi-useful designing group to execute and approve the actual plan on the parts of timing, region, dependability, testability, and power. Drive RTL-to-GDS course through amalgamation and spot and-course focusing on aggressive focuses for power, execution, and region while teaming up with computer-aided design group to foster actual plan philosophies; and running actual plan confirmation stream and fix format versus
